New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic

نویسندگان
چکیده

برای دانلود باید عضویت طلایی داشته باشید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Pico-Watt Source-Coupled Logic Circuits

This article explores the main tradeoffs in design of subthreshold source-couple logic (STSCL) circuits. It is shown analytically that the bias current of each STSCL gate can be reduced to few pico-amperes with a reliable logic operation. Measurements on different digital building blocks are provided to validate the main concepts presented in this paper. Implemented in conventional 0.18μm CMOS ...

متن کامل

Low Power Memory Design Using Source Coupled Logic

Design flexibility and power consumption in addition to the cost, have always been the most important issues in design of integrated circuits. Power dissipation and energy consumption are especially important when there is a limited amount of power budget or limited source of energy. Recently advances in VLSI Technology have made it possible to put a complete System on Chip (SOC) which facilita...

متن کامل

Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits

Subthreshold source-coupled logic (STSCL) circuits can be used in design of low-voltage and ultra-low power digital systems. This article introduces and analyzes new techniques for implementing complex digital systems using STSCL gates with an improved power-delay product (PDP) based on source-follower output stages. A test chip has been manufactured in a conventional digital 0.18μm CMOS techno...

متن کامل

A Minimal-Cost Inherent-Feedback Approach for Low-Power MRF-Based Logic Gates

The Markov random field (MRF) theory has been accepted as a highly effective framework for designing noise-tolerant nanometer digital VLSI circuits. In MRF-based design, proper feedback lines are used to control noise and keep the circuits in their valid states. However, this methodology has encountered two major problems that have limited the application of highly noise immune MRF-based circui...

متن کامل

A New CMOS Ternary Logic Design for Low-power Low-voltage Circuits

This paper shows a new approach to low-power low-voltage CMOS MultipleValued (MVL) Ternary Logic, the “complete model”. This logic uses standard technology processes and requires only an extra power supply more than binary CMOS circuits. Using an original characterisation of CMOS multivalued dynamic gates, it is shown as the advantages obtained are better noise margins and a lower power consump...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: Journal of Electrical and Computer Engineering

سال: 2011

ISSN: 2090-0147,2090-0155

DOI: 10.1155/2011/670508